1. Field of the Invention
The present invention relates to a partial product generating circuit which receives signals from a secondary Booth's encoder, selects multiplicands and outputs a partial product.
2. Description of the Related Art
As a secondary Booth's encoder, there is a circuit disclosed in Japanese Laid-Open Patent Application No. 7-160476 as an example of the Prior Art. This circuit has three predetermined places of bits of a multiplier Y input thereto, and outputs a signal 1X which indicates that a multiplicand X is multiplied by 1, a signal 2X which indicates that the multiplicand X is multiplied by 2, and a signal COMP (NEG) which indicates whether the multiplicand X is multiplied by a positive value or a negative value. As a partial product generating circuit which outputs a partial product using the outputs of a Booth's encoder, there is a circuit disclosed in Japanese Laid-Open Patent Application No. 7-160476 as an example of the Prior Art. This circuit includes three NAND gates and an XOR gate. This circuit has the signals 1X, 2X and COMP (NEG) input thereto, also has an arbitrary bit x.sub.i and an adjacent bit x.sub.i-1 less significant than the bit x.sub.i by one place of a multiplicand X input thereto, and outputs a partial product PP.
However, in the above-described partial product generating circuit, passing through three stages of gates, that is, the two stages of NAND gates and the one stage of an XOR gate, is required for generating a partial product for a multiplicand. Thereby, it is not possible to achieve high-speed partial product generation. Further, the power consumption is large.
In consideration of this point, Japanese Laid-Open Patent Application No. 7-160476 discloses partial product generating circuits using multiplexers. Specifically, an arrangement including three stages of multiplexers and arrangements each including two stages of multiplexers are disclosed.
However, in the arrangement including the three stages of multiplexers, passing through three stages of gates, that is, the three stages of multiplexers, is required for generating a partial product for a multiplicand. Thereby, it is not possible to achieve high-speed partial product generation. Further, in the arrangements each including the two stages of multiplexers, although it is possible to achieve high-speed partial product generation, because the number of pass transistors included in the multiplexers is large, the circuit scale is large.
Further, Japanese Laid-Open Patent Application No. 6-19685 also discloses a partial product generating circuit. The thus-disclosed partial product generating circuit is similar to the above-described arrangement including the NAND gates and the XOR gate. Therefore, it is not possible to achieve high-speed partial product generation, and, also, the power consumption is large.